1. Field of the Invention
The invention relates to a monolithically integrated test circuit for testing a digital semiconductor circuit configuration having a large number of elements to be tested. The test circuit is formed on the same semiconductor chip as the circuit configuration under test. The test circuit includes a read and write circuit for writing and reading a test data pattern to and from the elements to be tested, a comparison circuit, and a pattern variation circuit which can be activated by an activation signal.
When testing the operation of a semiconductor memory, as a particularly preferred embodiment of the semiconductor circuit configuration according to the invention, apart from the individual data and address lines, the memory cells are, in particular, checked with regard to manufacturing faults. Since large numbers of cells have to be tested when the semiconductor memories are still part of the wafer, they are generally addressed combined into groups, rather than individually. In such a compression test, the data bits are normally combined into groups and are connected to a smaller number of I/O interfaces (I/O=in-out) than the chip actually has. Depending on the chip architecture, one data bit is in each case written to a number of data lines when a write access is made via the small number of I/O interfaces. When a read access is made, the data bits of these data lines are checked in groups to ensure that they are equal, and the result of this test is output respectively as PASS or FAIL information to the small number of I/O interfaces. One disadvantage of this procedure is that it is impossible to write any desired number of data patterns to the memory, since the data lines that are combined all have a fixed polarity. Since the physical environment of the memory cells is different and can cause polarity-dependent failures, some defective memory cells are overlooked in such a "rigid" test. Such a test is thus useless, since even a single memory cell defect can lead to the entire component being scrapped. A further disadvantage of this procedure is that testing for equality in the situation where all the combined data bits are "wrong" can lead to a supposedly "correct" result.
U.S. Pat. No. 5,418,790 discloses a test circuit for detecting interference for a semiconductor memory apparatus which, for simultaneous investigation of memory cells, programs the memory cells simultaneously with a single test bit that is common to all the memory cells, and combines the determined data values stored on the basis of the test bit such that a check is carried out at the same time to confirm that all the data values are absolutely identical. Furthermore, the previously known apparatus has logic apparatuses which can be activated by a signal, and by which the test bit and the data values determined from the memory cells can be inverted simultaneously before they are combined. However, the previously known apparatus has the disadvantages mentioned above.